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Politics : Formerly About Advanced Micro Devices
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To: minnow68 who wrote (121220)7/30/2000 11:38:42 AM
From: Scumbria  Read Replies (1) of 1574306
 
Mike,

Wouldn't skew be smaller with the smaller die and latch delay reduced with the faster transistors?

The latch delay will be reduced with faster transistors, but clock issues will not scale as well. Intel has said that they are forwarding cache data on half cycle boundaries into the ALU. Can you imagine the clock skew issues they are faced with synchronizing between the cache and ALU at 4GHz?

Scumbria
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