Hi Dave B; Re: "Of course the argument will be made that if RDRAM can have 50% data valid window, then so can DDR. That's true, if they choose to implement more RDRAM technology in DDR. Already they've used differential clocks, small swing signals, and transmit DLL's. They could add receive DLL's, output driver calibration, matched impedence drivers - any number of things that are available from the Rambus patent portfolio that they seem to think they have free and unfettered access to. And, incidently, these are the same things that JEDEC is talking about incorporating into DDR-II."
Now I see how this particular wingnut is screwed up. He thinks that having the write data valid window (tS + tH) be a large percentage of the cycle time is a good thing. Nothing could be more incorrect.
This is going to be well beyond the understanding of the vast (unwashed) hordes who are likely to read this thread, but anyway...
The write data valid time for a memory (or any kind of register) is the time that the design must hold the input valid. The longer that valid time, the more difficult it is for the engineers to hold it that long. The best write data valid time is the shortest one, not the longest one. This wingnut is saying that larger percentages are better. No design engineer would make that sort of mistake.
The basic fact is that high speed interfaces are more difficult to engineer. This leads to higher expenses, more field failures, etc., etc., etc.
The simple fact is that if RDRAM were an easy memory to hook to, a lot more guys would have designed it into their equipment. But right now, the DDR chipsets on design boards outnumber RDRAM chipsets by about 4 to 1. Part of that is cost, but another contribution is the ease of design associated with DDR. Why do you guys think that Altera and Xilinx support DDR (and have for several years) but neither support RDRAM, nor have any announced plans to do so? RDRAM is a pain in the ath to use.
-- Carl |
