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Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 219.92

-4.5%

2:39 PM EST

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To: dale_laroy who wrote (3964)	8/9/2000 6:59:42 AM
From: Hans de Vries	Read Replies (1) of 275872

Dale. It's hard to believe that the Athlon doesn't use the critical word first. The 8 cycle latency from L1 miss to L2 data is most likely the result of keeping the whole bus/cache interface unmodified for the Thunderbird. This bus interface can handle clock-multipliers for L2 cache and therefor probably needs 2 registers between Processor and L2 cache both ways (Address out / Data in) This would explain 4 of the 8 cycles. The remaining 4 would then be the real L2 access time (L2 Tags, then L2 Ram) Probably the only thing which is modified in the Athlon Core is the L1 dirty bit which makes the L1 work as an Exclusive Cache when it is stuck to "1". BTW. Good to see you on this thread! (see also amd.com Regards, Hans

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