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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 230.23-4.3%Nov 18 3:59 PM EST
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To: Ali Chen who wrote (4208)8/10/2000 6:14:21 AM
From: BilowRead Replies (1) of 275872
 
Hi Ali Chen; Of course I agree with you that the 1GB/sec bw limit of the FSB is not a bottleneck for real applications.

But the context was a discussion of why there wasn't even much in the way of hyped up synthetic Intel benchmarks that showed 1.6GB/sec RDRAM doing much good. For someone writing those benchmarks, the FSB is a nasty bottleneck. (So they did goofy things with the AGP & PCI buses, if I remember correctly.)

I think there will be a (barely) measurable difference with single processors, about what you are saying, but when they put together 4 processors on the same single width memory channel, DDR should provide a significant difference.

-- Carl

P.S. I put a post here showing (more or less) how to estimate performance improvements assuming linearity in execution time. If you want to assume non linearity, it helps to know that the nonlinear results should be "convex". That is, a system that includes two improvements will run at least as well as the linear approximations based on adding the two improvements suggests. The reason for this is that the nonlinearities usually show up as maximum functions. That is, the actual time to complete some task is the longer of two subtasks rather than the sum.
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