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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 233.54-1.8%Nov 7 3:59 PM EST
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To: kash johal who wrote (4499)8/11/2000 1:26:58 AM
From: Paul EngelRead Replies (4) of 275872
 
Kash - Re: "Its probably pin limited - no wonder they doubled the l2 cache."

When bond pads had to be along the outer 4 edges of the die, pin limiting sometimes became a problem when the devices were shrunk, as you suggest.

However, with flip-chip mounting, the solder bumps can be distributed across the device - so it isn't clear this is why the doubled the cash size.

My guess, Intel wanted the performance boost - especially for lower cost XEON versions.

Re: "Do you have a die size estimate at 0.13."

My guess is it will be the same size as the current Coppermine (90 - 100 Sq. MM) since the process shrink is offset by doubling the L2 cache size.

Re: "What is earliest you see it introduced - is Q1 2001 feasible."

I doubt that is possible - the first silicon will have to be rock solid (possible ?) but the 0.13 micron process will probably need another quarter to get it into production readiness - to enable a clean transfer from TD to Manufacturing.

My guess is Mid Q2 2001 time frame.

I suspect that Intel would use this CPU as a feature article for next year's ISSCC (February) and that would imply that the intro will NOT be Q1 2001.

Paul
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