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Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 223.46

+4.3%

3:59 PM EST

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To: Joe NYC who wrote (5210)	8/16/2000 11:48:56 AM
From: jcholewa	Read Replies (1) of 275872

Jozef: (just a friendly FYI) > I think Pentium was the first one with pipeline architecture. 486 added L1 cache and more of the instructions were able to > execute in 1 cycle. uib.es "The Intel 486 also sports a RISC-like pipeline--no mean feat for a complex instruction-set computer (CISC) processor ... The stages of the 486 pipeline are Instruction Fetch, Instruction Decode, Address Generation, Execution, and Write Back." cs.nmsu.edu (PF --> D1 --> D2 --> EX --> WB ) byte.com "The IDT-C6's pipeline resembles a 486 pipeline." byte.com "Pipelining and less microcode allow the 486 to process many of its instructions at an effective rate of one instruction per clock cycle, compared to a dozen or more clock cycles required by earlier 80x86 chips. (RISC chips achieve the same result partly by using simpler instructions that inherently require fewer clock cycles.)" w3.tyenet.com "The 386 is a 'partially pipelined' processor with some optimizations. It checks for jumps ( A check) in a quite slow way and most of times can execute every stage in one cycle. It cannot perform the address generation check (B check) so it must execute stage 3 and 4 in 'not pipelined mode'. This explains why THE FASTEST 386 INSTRUCTIONS TAKE TWO CYCLES ( stage 3 unit must wait stage 4 to complete before managing the next instructions) ... The 486 has an improved EXECUTION unit (stage 4), improved memory access AND its control unit can perform the address generation check so that it can pipe stage 3 and 4 if there are no register/memory conflicts with two successive instructions. This explains why lots of 486 instructions take just one cycle (if the pipeline is filled and no pipeline stalls are produced). What's more, pipeline reloading is improved, so even jumps have less impact on execution time."

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