Another article. (Written in June)
icd.pennwellnet.com
Network-processor philosophies diverge
By Stephen Hardy
With emerging network-processor companies disappearing left and right
due to acquisition, a systems designer can be forgiven for feeling confused
about where to turn to meet new requirements. Such uncertainty may
grow if the divergent paths of two of these new suppliers signal the start
of a trend.
Interviewed at the recent GEC2000 event in San Jose, CA, marketing vice
president Charlie Jenkins of Solidum Systems Corp. (Scotts Valley, CA),
revealed that his firm has decided to focus its efforts on only one of the
major network-processing functions: classification preprocessing of
packets at OC-192 rates. In a presentation at the show, Jenkins said that
network processors offered an ideal solution to the challenge of
high-speed classification, which tends to be a laborious process that can
slow cycle times if left to the CPU. Jenkins says such processors can be
used in both centralized and distributed architectures, depending on the
system requirements.
Separately, Jenkins said that for high-speed applications such as 10 Gbits/
sec, the full range of network-processing functions would best be handled
by multiple processors. He said several different firms already have
processors that could handle pieces of the network-processing puzzle at
OC-192 rates. Solidum will seek to partner with these vendors and others
to provide classification capability for a range of applications.
The company recently inked a deal with Sitera Inc., another
network-processor vendor, to pair their two offerings. The Solidum chip
will perform complex policy identification tasks, freeing Sitera's chip for
application processing. The company also has aligned with Quantum Effect
Devices Inc. (QED-Santa Clara, CA) to provide classification capability
alongside QED's RM7000 microprocessor for OC-192 line-card applications.
At Networld + Interop, Solidum also announced an agreement with Vitesse
Semiconductor Corp. (Camarillo, CA) to pair its classification technology
with Vitesse's TeraPOWER architecture for OC-192 applications. In
addition, Solidum unveiled PAX.port 1100, a 16-channel classifier design to
support aggregate classification rates from 1.6 to >5 Gits/sec. The chip is
slated for sampling this September.
But while Solidum and others take a multichip approach to high-speed net
work processing, EZchip Technologies (Migdal Haemek, Israel) thinks one
chip is enough. The startup company has unveiled the core technology
that it says will enable 10-Gbit/sec, seven-layer, wire-speed packet
processing in a single device.
The technology, called Task Opti mized Processing Core (TOPcore),
represents an evolutionary advance over the RISC-based architectures
used in some network-processor offerings, says Eli Fruchter, EZchip's
president and CEO. The architecture consists of several small, high-speed
processors, each optimized for a specific task, contained within a single
chip. The processors are connected in parallel and pipeline to improve
performance; embedded memory also improves efficiency.
The results, says Fruchter, significantly reduce the time required to
perform processing tasks. For example, the forthcoming EZchip products
will be able to parse a URL in an HTTP/RTSP packet in 60 clocks, search
URL tables in six clocks, and resolve a multicast routing decision in eight
clocks. The architecture also will enable the chip to draw information from
the entire contents of a packet to perform content switching to support
multiple quality-of-service or service-level agreements, as well as
applications such as voice over Internet protocol. Fruchter says that the
initial chip's 1x10-Gbit/sec and 8x1-Gbit/ sec port sizes should scale to
128x10 Gbits/sec and 1,024x1 Gbit/sec. Prototypes should be available by
March of next year, with volume production scheduled for June 2001. |
