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Technology Stocks : Intel Corporation (INTC)

INTC 36.26

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Dec 18 3:59 PM EST

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To: Cirruslvr who wrote (107834)	8/21/2000 3:24:46 AM
From: Scumbria	Read Replies (1) of 186894

Cirrus, "L1 data cache may be small for a very good reason: high clock speeds." This guy azillionmonkeys.com thinks its latency will be 2 clocks vs. PIII and Athlon's 3 clocks, so I guess that will help make up for the L1 data cache being comparatively small. In an x86 pipeline, the absolute latency of the L1 cache is not very important. This is because almost every instruction requires at least one L1 read, so the pipeline can be kept full. What is important is the hit rate, which is where a small cache will suffer. If the 8K 2-cycle data cache is correct, the Willy architects seem to have made a critical error which will impact IPC and frequency. Willy is starting to sound like another Intel boondoggle. Scumbria

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