Actually Carl,
I would have thought that the gloating would have been over your uncanny demolition of the "DRDRAM in OC-192" myth back in the wee hours. Or do you have a secret source in Palo Alto?
eetimes.com
Bob Merritt, director of emerging markets for market analysts Semico Research Corp., said Entridia's approach has some strengths but advised that the company pay attention to details beyond the purely technological. "This idea definitely has some routing advantages, but the disadvantage is that the communications industry has always been paranoid of using sole-source chips," he said. "Communications is heavily regulated by the government and is almost considered a national resource. They will be reluctant to support a technology if there's only one vendor providing the chips."
One key to Entridia's design is its memory architecture, which features an on-die cache using a 128-bit-wide bus. Several other network processors also have used wide memory buses to increase on-chip data transfers.
Mike O'Connor, director of advanced architecture for Silicon Access Networks, said that more than 70 percent of his company's iFlow address processor is embedded DRAM, which is used to speed the lookup phase (during which a routing engine compares the address in a packet to addresses stored in a lookup table to determine where to send the data).
Indeed, the key to Silicon Access Networks' approach is not just the on-die cache but the use of memory blocks with exceptionally wide custom DRAM, which allows for faster communication within the chip, O'Connor said. Besides 1.2 Mbits of SRAM, with a width exceeding 2,000 bits, the iFlow packs 52 Mbits of DRAM, in three different configurations. Two Mbits feature blocks 256 bits wide running at 133MHz; 25 Mbits run at the same speed but are 100 bits wide; and the final 25 Mbits are slower, running at 66 MHz, but are 3,200 bits wide. O'Connor said that the total aggregate bandwidth for the memory is 252 Gbits/s.
The chip can support systems running at OC-192 rates, and up to four of the devices can be implemented in a cascade structure. The iFlow will be fabricated in a 0.18-micron process at Taiwan Semiconductor Manufacturing Co. Ltd. and is slated to be available next year.
Imagine and not a reference to DRDRAM or RMBS to be found. ...I guess they are still working on that new embedded DRAM patent. :8)
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