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Technology Stocks : Intel Corporation (INTC)

INTC 33.62

-4.2%

Nov 20 3:59 PM EST

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To: pgerassi who wrote (108233)	8/24/2000 1:41:51 PM
From: Tenchusatsu	Read Replies (1) of 186894

Pete, you are amazing. You really do sound like you know what you are talking about. Here's an example: <This is borne out by the Huge size of the trace cache. Originally it was supposed to be no more than a few hundred micro ops. It has since ballooned to 12 thousand ops. This is probably why the die expanded from 170 mm2 to 217 mm2.> Wow, I never knew there was such an increase in die size. (And I thought at least one of those figures was just wild speculation by the press.) I also never knew about the increase in the trace cache size, or the "fact" that it was supposed to be no more than a few hundred micro-ops. Here's another: <This means that the original design goal for IPC or a 10 to 20% loss in IPC was much higher in practice. It was probably more like 30 to 50% loss. > Only someone who was involved in the Willamette design and validation would ever know all this. Once again, Pete, you are amazing. Tenchusatsu P.S. - How come you don't know half as much about the Athlon architecture, given that you are an AMD fan?

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