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Technology Stocks : Intel Corporation (INTC)

INTC 35.10

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Nov 19 3:59 PM EST

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To: Proud_Infidel who wrote (108225)	8/24/2000 3:10:46 PM
From: EricRR	Read Replies (1) of 186894

Tench- What do you think: Jeff Austin, Intel's IA-32 architect launch manager, said the Pentium 4's 20-stage pipeline suffers no penalty for pre-fetch misprediction because of its use of the NetBurst technology A is "prefetch" misprediction the same as a general "branch" misprediction penalty? As I understand it, prefetch is where a specific piece of code or data is requested into the cache before it is needed, in anticipation of its imminent requirement. Is the above quote just "spin" on the idea that the branch mispredict for code in the trace cache will only be 20 clocks, vs 26 for code outside the trace? (BTW are those numbers right?) Did you say yesterday that P3 has a 13 clock mispredict penalty? Or was that total pipe size? Sounds to me like Intel is setting themselves up for more polymorphic code problems, which by their nature have high mispredict rates. Are Willimettes decoders really insuffient to supply the pipe without trace cache micro-op reuse? This the opposite of what you want for servercode. Intel makes great compilers (i'm using one right now!) but they missed the boat on the future of software design.

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