Daniel, >The one thing that's a real head scratcher is putting this double-clocked alu in the middle of the ultra deep pipeline, where it seems to have a good chance of holding down the maximum clock speed for at best marginal performance enhancement. I'd assume that was a pure engineering decision too, if Intel lets marketroids make architectural decisions like that, they're really hosed.
I believe Intel has said that the double frequency ALU is only for some instructions, undoubtedly the simpler ones. From my logic design days, some instructions, like XORs, adds, etc., can be done in only one or two levels of logic. Using the fastest macros available for these logic levels, it could be that running the ALU that executes those instructions, at 2F, will not be a bottleneck, because of these reasons.
I have to say that a lot of conclusions have been jumped to around here lately about the P4. Not doubting the expertise represented here at all, but the speculation is running way high.
Tony |
