SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 243.98+4.5%Nov 10 3:59 PM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Scumbria who wrote (7267)9/1/2000 10:45:04 AM
From: Daniel SchuhRead Replies (2) of 275872
 
Scumbria, this brings to mind another question for Bilow or you. You've both talked about eDRAM, but it doesn't seem to be mentioned much in the context of mainstream processors. Is there a process reason for that? I can understand it wouldn't work for L1 cache, but maybe L2 or on-chip L3? Or is it just too complicated to manage? My naive impression is that DRAM is at least 4x as dense as the SRAM used for caches, so going to an on-chip L3 eDRAM cache might more efficient than the super-large L2 caches in Xeon/Mustang type processors, anyway.

Cheers, Dan.
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext