SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 215.00+0.7%Dec 22 3:59 PM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: Bilow who wrote (7399)9/2/2000 6:04:48 PM
From: TechieGuy-altRead Replies (1) of 275872
 
I could easily design a 32-bit adder that had only two stages of even simple NAND gates. Just make a Karnaugh map for the function, and decode it into sum of products. A computer would be useful for doing this. Of course I would have to
use NAND gates with a couple thousand inputs...


(dusting off my old VLSI design hat): Actually, from what I remember, in such an adder, the carry would have to ripple over. That's the last thing that you want if you want to do a quick add. I doubt that the carry bit could ripple through your 32 "single stage" adders in any reasonable amount of time.

What you need is a look ahead carry adder (of some sort), and that would take more than 2 stages.

JMHO
TG
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext