Geek time!
From the Merrill Lynch report dated 9/5/2000:
Technology
McDATA has developed ASIC technology that serves as the foundation for a
complete family of SAN products. Its ASICs provide building blocks at the
circuit level for implementing fibre channel technology. These ASICs combine a
number of fibre channel functions in a single chip and thereby substantially reduce
the number of components needed in its fibre channel switches. McDATA’s
design expertise in fibre channel and storage area network allow it to deploy best-of-
class high availability fibre channel switches.
Using these ASICs, McDATA has developed and is currently testing its next
generation switch implementation based on a new cut-through switch
architecture that uses a common hardware and software design. The
architecture allows product designs that span the high-end and midrange
computing environments requiring gigabit performance while providing 24x7
operation and switched fabrics allowing SAN installations that scale beyond
8000 ports.
This second generation of FC SAN products provide the largest single stage
switch in the industry. In addition to the support for full duplex, 1.0625 Gbps ports
at low latencies over Class 2 and 3 connections, the design supports 2.125 Gbps and
future 10 Gbps links. This high performance non-blocking design is achieved
through the use of Source Port Buffering, with Virtual Output Queuing (VOQ).
This technique avoids head of queue blocking and port bandwidth issues.
As with McDATA’s first generation fibre channel products, the significant
reliability, availability, manageability, and serviceability (RAS) characteristics of
the product are key design elements of the next generation switch products. These
characteristics include the following:
Key Technology Aspects Benefits
edited
McDATA’s software product architecture is based on an in-house embedded real-time
operating system that provides state-of-the-art RAS characteristics. The
software design delivers ANSI compliant fibre channel services for the entire
family of SAN products, using a single, common code image.
[end of ML excerpt]
What is cut-and-switch?
This is an excerpt from a previous post that explains this technology.
....ASICs can perform cut-through forwarding of frames based on MAC destination or Fibre Channel fabric addresses. A crosspoint switch matrix is a single ASIC that creates dedicated physical paths between any input port and the destination output port. It scales well and does not require the buffering of store-and-forward.
Cut-Through and Store-and-Forward
Two architectures determine switching applications and performance: cut-through and store-and-forward.
Cut-through switching starts sending packets as soon as they enter a switch and their destination address is read (within the first 20-30 bytes of the frame). The entire frame is not received before a switch begins forwarding it to the destination port. This reduces transmission latency between ports, but it can propagate bad packets and broadcast storms to the destination port.
Store-and-forward switching, a function traditionally performed by Ethernet bridges and routers, buffers incoming packets in memory until they are fully received and a cyclic redundancy check (CRC) is run. Buffered memory adds latency to the processing time and increases in proportion to the frame size. This latency reduces bad packets and collisions that can adversely effect the overall performance of the segment.
Some switches perform on both levels. They begin with cut-through switching, and through CRCs they monitor the number of errors that occur. When that number reaches a certain point, a threshold, they become store-and-forward switches. They remain so until the number of errors declines, then they change back to cut-through. This type of switching is called threshold detection or adaptive switching.
Message 14255227
What is Source Port Buffering with Virtual Output Queuing?
This is an excerpt from a recently issued McDATA patent that provides a basic description of the performance gap that this technology addresses.
.....The Fibre Channel industry standard also provides for several different types of data transfers. A class 1 transfer requires circuit switching, i.e., a reserved data path through the network switch, and generally involves the transfer of more than one frame, oftentimes numerous frames, between two identified network elements. In contrast, a class 2 transfer requires allocation of a path through the network switch for each transfer of a single frame from one network element to another. Frame switching for class 2 transfers is more difficult to implement than class 1 circuit switching as frame switching requires a memory mechanism for temporarily storing incoming frames in a source queue prior to their routing to a destination port, or a destination queue at a destination port. A memory mechanism typically includes numerous input/output (I/O) connections with associated support circuitry and queuing logic. Additional complexity and hardware is required when channels carrying data at different bit rates are to be interfaced.
It is known to employ centralized queuing that is inherently slow as a common block of logic must be employed for all routing decisions within the switch.
It is also known to employ distributed source queuing which has apparent disadvantages when the frame at the head of the queue is destined to a port that is already forwarding a frame such that the path is blocked and the frame cannot be transferred. Alternatively, it is known to employ distributed destination queuing, which has the apparent disadvantage of a large destination queue at each port as it is possible for all frames within the switch to be simultaneously queued to the same destination port.
Another disadvantage of distributed destination queuing is apparent when the frame at the end of the head of the queue is sourced from a port that is already forwarding a frame such that the path is blocked and the frame cannot be transferred.
Thus, a heretofore unaddressed need exists in the industry for new and improved systems for implementing the Fibre Channel industry standard for transfers on fiber optic networks with much higher performance and flexibility than presently existing systems. Particularly, there is a significant need for a method and apparatus that combines both distributed source and destination queuing in a high performance memory based switch. A need also exists to implement distributed queues between the source and destination ports, requiring the lower queue storage resources of source queuing, but providing the high throughput of destination queuing and avoiding "head-of-line" blocking of either source or destination queuing.
It would be desirable and of considerable advantage to provide a Fibre channel switch that provides for efficient transfer of queuing information between Fibre channel ports, especially if the new switch provided an improvement in any of the following areas: increased bandwidth, decreased no-load latency and increased throughput under load (due to parallelism of distributed queuing).
It will be apparent from the foregoing that there is still a need for a High-Bandwidth memory-based switch employing distributed queuing that differs from that employed in existing centralized Fibre Channel switch architectures. In addition there is a need for a method and apparatus for reducing the data path latency and the minimum inter-frame delay normally associated with time slicing and bit slicing shared memory switches.
United States Patent 6,031,842
Low latency shared memory switch architecture
Assignee: McDATA Corporation
Inventors: Trevitt, et al.
Application date: November 26, 1997
Issue date: February 29, 2000
164.195.100.11 |
