The road to wafer-level packaging diverges
Sep. 15, 2000 (Electronic Engineering Times - CMP via COMTEX) -- TAIPEI, TAIWAN
- Amid industry efforts to develop wafer-level back-end technologies, FormFactor
Inc. and a group of companies formed at Semicon Taiwan last week are taking
distinctly different approaches. While FormFactor (Livermore, Calif.) has
licensed its proprietary MicroSpring technology to Hyundai Electronics
Industries Co. (Seoul, South Korea), the Semiconductor Equipment Consortium for
Advanced Packaging (Secap) is striving to develop open standards for wafer-level
packaging.
FormFactor CEO Igor Khandros said his company's approach is more comprehensive
than wafer-level packaging. The company's goal is to replace the conventional
back end-which packages, burns in and tests singulated die-with a wafer-level
process that would perform all the major back-end steps across the entire wafer.
Secap, which was launched at Semicon Taiwan by a group of
semiconductor-production equipment and materials suppliers, aims to develop
advanced wafer-bumping and wafer-level packaging technologies for 300-mm silicon
substrates.
Secap's organizers said the group will enable member companies to share data,
define process and tool interfaces, and jointly develop road maps for advanced
bumping and wafer-level packaging technologies.
Application process center
The Fraunhofer Institute (Berlin), a research and development organization, will
set up an application process center for the consortium, which includes Image
Technology, Karl Suss, Semitool, Unaxis (formerly Balzers Process Systems) and
the Fraunhofer Institute for Reliability and Microintegration IZM.
The effort to develop wafer-level back-end technologies could resemble what is
happening in the DRAM industry, where Rambus Inc. (Mountain View, Calif.), which
licenses its patented technology, is competing against technologies standardized
within Jedec, the standards body for the memory industry.
FormFactor may well have a head start over the slower-moving consortium
approach. And like Rambus, its technology is guarded by 125 patents, either
granted or pending.
FormFactor has also licensed its technology to Japanese packaging powerhouse
Shinko Denki.
Efforts to develop advanced packaging and test technologies are being made
throughout the industry. Companies with high-volume products, ranging from
Toshiba Corp. to Motorola, are especially interested, and are working
individually on wafer-level packaging and test techniques. Two years ago,
Motorola and Tokyo Electron Corp. announced that they had developed a
wafer-level probe technology that Motorola uses for its high-lead-count
packages.
Concept at work
FormFactor's MicroSpring concept has been proved out in its bread-and-butter
business: probe cards that use the springs to probe finished wafers for known
good die. The active probe head is four inches in diameter and can test 128
DRAMs in parallel.The probe cards have demonstrated the MicroSpring's
durability: Each card must withstand millions of cycles, and a single defective
contact results in good die being reported as no good.
Khandros said the MicroSprings on the probe head are at 70- to 80-micron
center-to-center spacings, which compares with the 25- to 30-mil pitch for chips
placed on a printed-circuit board.
The approach uses the MicroSprings attached to the die substrate as the contacts
for probers and high-speed testers, as well as for the interconnect between the
die and the memory module. Though the spacings on the springs can be small
enough to accommodate high I/O ASICs, the technology currently supports lead
counts of 300 or less.
The MicroSprings are electroplated across the wafer, replacing the solder balls
used in flip-chip packages.
Khandros said FormFactor, with 250 employees and 1999 revenue of $36 million,
aims "to pour our licensable technology into a very large market, the back end
of the semiconductor industry."
Farhad Tabrizi, vice president of strategic marketing at Hyundai, said Hyundai
will license both the wafer-level packaging and test technologies and apply them
to its high-bandwidth DRAM products. Besides reducing costs, the approach will
improve the reliability of the memory modules, he said.
Because the die can be soldered to the substrate of the memory module with no
need for an underfill material, or socketed in to the substrate, the electrical
performance and reliability of the process are superior to the solder-ball
approach in conventional chip-scale packages, Khandros said.
"We want to streamline the back end, apply the same scalable logic there as
applies to the front end. To do that the industry has to go beyond wafer-scale
packaging, to include wafer-level burn-in, some long-cycle testing and full-spec
final testing while still on the wafer. We want to apply the same kind of
scaling, and to do that we have to solve all three," Khandros said.
Cost-cutting measures
"The percentage [of costs] of the back end is going up, and we need to drive
that back down by integrating the front end and the back. By handling the whole
wafer, instead of the single dice, we can get much lower costs," he said.
Shinko Denki (Nagano, Japan), which is affiliated with Fujitsu Ltd., is working
with several semiconductor companies that are evaluating the FormFactor
approach.
Shinko Denki has a license from FormFactor to do contract assembly and plans to
offer module assembly as well. "Others will use Shinko Denki for contract
assembly and test," Khandros said.
Hyundai's Tabrizi said the high-volume DRAM industry may benefit from the faster
feedback cycles possible with wafer-level back end. Today, the wafers are sawed,
packaged, picked into carriers for burn-in and again into test carriers for
testing. The carriers for burn-in and test are fairly large, requiring larger
burn-in ovens, larger facilities and expensive pick-and-place machinery.
With a wafer-level back end, valuable information from the probe, burn-in and
test cycles can quickly be relayed back to the front-end process. That will
result in improved yields and faster binning of chips as they are sorted into
speed grades.
MARK LAPEDUS IS A SILICON VALLEY-BASED REPORTER FOR SEMICONDUCTOR BUSINESS NEWS
(SEMIBIZNEWS.COM), AN ONLINE SISTER PUBLICATION TO EE TIMES.
eetimes.com |
