TAEC takes aim at system ICs
Sep. 22, 2000 (Electronic Buyers News - CMP via COMTEX) -- Silicon Valley-Toshiba America Electronic Components Inc. is piecing together a system-level integration portfolio it hopes will raise its profile at U.S.-based
communications-infrastructure OEMs.
Under-leveraged by its own lights, TAEC, based in Irvine, Calif., has recently been given more autonomy by its Japanese parent to pursue fast-growing markets,
such as digital consumer and optical networking. Though it continues to rely on Toshiba Corp.'s prowess in semiconductor processing, heavy investment this year
in IP, tools, and packaging will allow TAEC to offer by next year a more complete menu of system-IC options tailored for high-speed-networking customers,
according to company executives.
With Toshiba's 0.11-micron CMOS3 process technology as a base, TAEC plans to offer a family of I/O cells to support 10-Gbit/s chip speeds, fast and dense
DRAM cores, an improved design flow, and packaging that supports thousands of pins.
Will it be enough to elevate Toshiba-the eighth-largest ASIC supplier-into the ranks of IBM, LSI Logic, and Lucent, which have recently made high-profile moves
to bolster their positions in the communications market? Analysts aren't yet sold.
"Toshiba's definitely investing money in all the right places to capture networking business, but competition is fierce," said Bryan Lewis, an analyst at
Dataquest Inc., San Jose. "It's harder now to differentiate on process technology. That's why they're pushing the system story."
And with good reason. The available market for communications ASICs and ASSPs is
estimated at some $11 billion this year, and will surpass $32 billion by 2004, according to Dataquest.
A critical piece still missing from TAEC's communications play is a well-rounded embedded-processor strategy, Lewis said. TAEC, which currently offers customized MIPS cores and standard products, said it expects within three months to define its processor road map to support both its networking and digital-consumer thrusts.
In the meantime, Toshiba's CMOS3 process, expected to start production in 18
months, will give customers high-speed and low-power I/O and library options,
while making it possible to integrate more than 10 million gates, TAEC said.
While 0.11-micron transistors will give a density and performance boost to
networking designs, high-speed I/Os are needed to move data on and off the chip
without creating system latency. Indeed, as chip manufacturers have raced to
bring copper and low-k dielectric processes to market to enable faster, denser
chips, I/Os have become the bottleneck, said Bill McClean, an analyst at IC
Insights Inc., Scottsdale, Ariz.
"When you've got massive switching systems where everything isn't on one board,
or data is moving between systems, I/O becomes extremely important," McClean
said.
To address this, TAEC is adding a 2.5-Gbit/s Sonet I/O cell to its standard-cell
library. The Sonet serializer/deserializer is the first in a planned family of
cells to support optical rates, Gigabit Ethernet, Fibre Channel, and other
emerging high-speed networking standards.
High-speed interfaces are not new to TAEC-or any of the leading ASIC and
system-on-a-chip vendors. But being able to put them on-chip is, said Peter
Richmond, business development director at TAEC's System IC business unit in
Milpitas, Calif.
"It's a new direction for Toshiba, and everybody in the ASIC business, " he
said. However, "it's a combination of these high-speed I/O cells, our embedded
[DRAM], and transistor density that sets us apart."
It may be embedded DRAM that gives TAEC a leg up, analysts said. Of its three
largest competitors, only IBM today has embedded-DRAM capability to rival
Toshiba's. Though it's been slow to take off, Dataquest expects embedded-DRAM
demand to double during the next two years. "That puts [TAEC] in a strong
position," Lewis said.
TAEC is further expanding its embedded-DRAM offering with 12-ns Fast Access DRAM
cores in 2- and 4-Mbit sizes. Designed as a high-density replacement for SRAM,
the FA-DRAM can be mixed with SRAM or SDRAM cores. Toshiba is also offering a
Direct Rambus ASIC cell for off-chip Rambus memory.
Additionally, the company has upgraded its Timing-Driven Flow to decrease the
design time for multimillion-gate chips by adding support for block and
chip-level design, with accurate 3D timing models.
New BGA packaging options are also being introduced to target specific
performance needs. Enhanced BGAs with 352 to 540 pins address thermal and
electrical requirements; TabBGAs with 256 to 960 pins represent the economy
model; and flip-chip BGAs offer the highest pin count, from 504 to 1,849 pins.
ebnonline.com |
