Thanks Don Green. As usual you have brought us food for thought and grist for the mill. :8)
With Toshiba's 0.11-micron CMOS3 process technology as a base, TAEC plans to offer a family of I/O cells to support 10-Gbit/s chip speeds, fast and dense DRAM cores, an improved design flow, and packaging that supports thousands of pins.
Hmmm,... "thousands of pins" ...I think its time that we came up with a comparable "Mom & Pop" moniker for EEs who have a tough time with their "vision" thingy and bring us such things as RDRAM and Beta Max!
"It's a new direction for Toshiba, and everybody in the ASIC business," he said. However, "it's a combination of these high-speed I/O cells, our embedded [DRAM],and transistor density that sets us apart."
What an odd thing for the cutting edge subsidiary of the first DRDRAM Faber to say. ...And a scant matter of months after "Daddy" signed up to feed the increasingly litigious RMBeaSt. My, my. ...It certainly appears that Toshiba has found a slightly different use for Sun Tsu than our Richard would suggest.
TAEC is further expanding its embedded-DRAM offering with 12-ns Fast Access DRAM cores in 2- and 4-Mbit sizes. Designed as a high-density replacement for SRAM, the FA-DRAM can be mixed with SRAM or SDRAM cores. Toshiba is also offering a Direct Rambus ASIC cell for off-chip Rambus memory.
There is a deep flowing current of irony, or perhaps I should say "sheet metally", in these words. "To get on the chip you must first get off the Bus." Yes many are offered, but few are sold. ...Which brings to mind a proper name for those EEs who have been lead astray.
I nominate "Emperor EEs" in honor of the "new clothes" they think they are wearing. :8)
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