Bilow, does this make any sense?
The entire pose below from the FOOL
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Artie,
Another likely cost adder is the extra shielding to overcome radio frequency emissions."
This may be a dumb question, but the last line caught my attention. Could complying with FCC Part 95 regulations also be a factor in cost / stability issues for DDR as a main memory solution?
this is one of the reasons i always like to see pictures of the working prototypes, etc. If DDR needs shielding it will be evident in the pictures. AL foil is a reasonable shield for EMI. So if you see anything like that in the DRR mobo picture that's a clue for EMI issues. Remember, there is two sides to EMI. One is DDR maybe a source for EMI. Another, DDR maybe affected by EMI noise source, such as the cable that runs from the mobo to the hard disc. BTW, this is IMO why INTEL is moving to the ATA-serial system between the mobo and HD. ATA-serial uses a shielded twisted pair cable that can handle EMI better than the gray cable that is presently used. Also note: from some on my readings of INTEL's literature, they recommend that the external cables wires,etc. be placed on the outside of the mobo. In other words, increase the distance of potential EMI sources from high speed CPU, memory etc. to reduce noise in the system.
DDR uses a signaling technique called SSTL, which I believe is short for Small Signal Transistor Logic. This signaling technique is IMO inferior to Low voltage differential signaling (LVDS) which is kinda what Rambus uses for handling noise in high-speed circuitry.
SSTL doesn't use differential signaling techniques to determine its digital logic levels. As I've already discussed, differential signaling greatly eliminates common mode noise. SSTL uses thresholding techniques to reject noise in the system. That is to say, a logic level "1" for SSTL is not just 2.5 volt, but any voltage over 2.0 volts (? Please don't hold me to the exact threshold volts). A logic level "0" is any voltage below 0.5 volts. SSTL has a voltage gap of 1.5 volts (?) so that a noise source won't accidently trip the logic level into the wrong state. So this is one of the way that SSTL handles noise (EMI).
The problem with this technique is that by spreading the voltage levels apart to handle noise sources, you have a relative large voltage swing (2.5 volts). As I already discussed, large voltage swings adds to ground bounce signals at high frequencies due to the slight inductance in the ground plane.
Recap: LVDS (similar to Rambus signaling techniques) superior design to SSTL for handling noise/EMI at high frequencies.
If this doesn't make sense to anybody, I'm sorry, but I just felt the need to share it with the board. |
