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Politics : Formerly About Advanced Micro Devices
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To: Tenchusatsu who wrote (125094)10/1/2000 10:19:52 AM
From: TechieGuy-alt  Read Replies (1) of 1571057
 
Tenchusatsu, there is a very good (technical) article in the Aug 21, 2000 print issue of Electronic design. I'll post a few points that it makes that I have not seen posted here before:

* Packets sent over the [LDT] interface use the standard plug&play headers. The system works with old, present and potential [future] operating systems.

* data send over LDT are sent using an async clock forwarding scheme, with one clock signal for every 8 bits of data in every direction.
[My comment: This is actually very smart, as one needs to keep the length of all the data lines (2 lines/bit) and clock for those lines matched to within 50-100mills at 800MHz. This would become very difficult to do with one clock per 32 bits (64 lines), just from a routable standpoint on the board. This way, only 18 lines need to be length matched on the board. Someone had their thinking cap on.]

* Even interrupts are handled via packets, rather than hardwired signals.
[My comment: Again very smart, as the design can never run out of interrrupts, and can support as many interrupts as a future remote LDT chip needs. You do of course pay a penality in terms of latency, especially if the LDT link is being bridged over multiple bridges.]

* For short distance CPU-CPU connections a dual 32bit (800MHz) clocked LDT interface can deliver an aggregate bandwidth of 12.8 GB/s which is 96 times 32bit/33MHz PCI.

TG

[Edit: I found a web link for the artcile. It seems to be missing 2 figures, but most of the text seems to be there.
elecdesign.com
]
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