Tenchusatsu, RE:LDT
I gather from reading the progress of the press releases, that LDT started as a scheme for connecting a north and south bridge together since a PCI interconnect is running out of steam. The idea being that each PCI, AGP and other bus would hook into a 4 to 32 bit LDT port. Once the design process got underway, they realized that it could do a lot more, like NUMA. And then it occurred to them that it could even be used as a PCI replacement. Heck, if they were so inclined, it could even be used as a memory bus, and solve a lot of the Rambus problems, to boot.
According to what has been released, Sledgehammer will have an integrated DDR memory controller and LDT bus(ses). At least a LDT and likely a cLDT also. LDT, and it's derivatives, is a real exciting way to handle I/O, the only question is how will the actual silicon work?
AMD had a good presentation at the Platform2000 conference, I'll try to dig up the link. |
