Monday October 2, 9:01 am Eastern Time
Press Release
SOURCE: Mentor Graphics Corporation
Mentor Graphics Announces BSDArchitect New Edition
Boundary Scan Tool Supports Test of Complex SoCs
INTERNATIONAL TEST CONFERENCE, ATLANTIC CITY, N.J., Oct. 2 /PRNewswire/ -- Strengthening its lead in the area of system-on-chip (SoC) design and verification, Mentor Graphics Corporation (Nasdaq: MENT - news) today announced BSDArchitect(TM) New Edition, an updated version of its Design-for-Test (DFT) boundary scan synthesis tool. BSDArchitect New Edition saves weeks in the design, verification and test of application-specific integrated circuits (ASICs), integrated circuits (ICs) and SoCs. Replacing the current edition of Mentor's BSDArchitect tool, BSDArchitect New Edition was completely redesigned to meet the new challenges of testing complex ICs and provide full integration into complete DFT flows such as automatic test pattern generation (ATPG) and built-in self test (BIST).
Driven by the increased complexity of printed circuit board (PCB) and packaging design technology, boundary scan has become the standard methodology for testing of complex PCBs. According to Prime Research Group(1), an estimated 42% of all designs will include boundary scan in the year 2000. Furthermore, with the migration to large SoC designs with internal and third-party IP, embedded memories and embedded software, boundary scan is now required to control complex test functions such as internal scan, BIST, and system debug.
Reduced Time to Market
BSDArchitect New Edition automatically generates an IEEE 1149.1 compliant test controller and boundary scan circuitry, allowing designers to dramatically reduce the amount of time and resources that would be required to manually implement the circuitry. By automatically generating the circuitry to the user's specification, design iterations can be updated in a matter of seconds.
``We have been using BSDArchitect New Edition for the past several months, and the tool has substantially decreased our chip integration time,'' said Joseph Vaccaro, DFT engineering manager for the DSP Standard Products division, Motorola Inc, based in Phoenix, AZ. ``In a dynamic system-on-chip design environment, design specifications and pinout configurations frequently change, and using BSDArchitect New Edition dramatically eased the pain of re-implementing the boundary scan.''
Completely Flexible Architecture
BSDArchitect New Edition generates synthesizable RTL descriptions of the boundary scan circuitry, Boundary Scan Description Language (BSDL) files and verification testbench. The tool supports a fully flexible architecture, generating circuitry to support any combination of boundary scan, including private instructions. This allows support of any configuration of boundary scan, from the simplest implementations for board-level test to a full SoC test controller for internal test, manufacturing test and software debug.
``BSDArchitect New Edition has been proven to dramatically improve designer productivity for incorporating boundary scan circuitry into highly complex SoC designs,'' said Fred Cohen, general manager, Design-for-Test division, Mentor Graphics. ``With its flexible architecture, new capabilities and integration with both ATPG and BIST DFT flows, BSDArchitect New Edition is meeting these new design challenges, while providing both high product quality and reduced time-to-market.''
Enhanced Capabilities
BSDArchitect New Edition also offers many new enhancements that provide designers with the most complete boundary scan logic tool in the industry. These include:
-- Automatic synthesis of the design's IO pads to further reduce the ASIC
implementation time.
-- Support of complex IO pads such as open collector outputs and
low-voltage differential inputs and outputs.
-- Automatic generation of DC parametric tests.
-- Direct control of memory BIST architectures, including Mentor's
MBISTArchitect and Memory BIST-In-Place.
Pricing and Availability
BSDArchitect New Edition is available immediately. The tool is priced at $50,000 and is supported on Sun Solaris and Hewlett-Packard HP-UX operating systems. Existing customers of BSDArchitect can upgrade to BSDArchitect New Edition free of charge. For additional information regarding BSDArchitect or any of Mentor Graphics ATPG and BIST tools, please visit the Design-for-Test web site at www.mentor.com/dft.
About Mentor Graphics
Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products and consulting services for the world's largest electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of more than $500 million and employs approximately 2,600 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777, Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com.
NOTE: Mentor Graphics is a registered trademark of Mentor Graphics Corporation. BSDArchitect is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
Mentor Graphics can be found in booth # 809 at the International Test Conference
(1) BIST User Study, Prime Research Group, June 15, 2000
CONTACT: Leanne White of Mentor Graphics Corporation, 503-685-1984, or leanne_white@mentor.com; or Jason Khoury of Benjamin Group/BSMG Worldwide, 415-352-2628, or jason@benjamingroup.com, for Mentor Graphics Corporation.
SOURCE: Mentor Graphics Corporation |
