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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 207.67+2.2%Jan 12 3:59 PM EST
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To: combjelly who wrote (11146)10/2/2000 5:09:08 PM
From: pgerassiRead Replies (1) of 275872
 
Dear Combjelly:

Regarding latency issues on LDT connected Nortbridges:

It depends on the size of the data being passed. If its one word, the latency is really bad. If it is the size of K7 cache line or 8 words, the latency would be say 2 cycles at FSB speed per LDT transversed (1 link both ways). If it was say a standard Linux memory page at 4K bytes (512 words), the latency would be minor.

It also depends on what is needed as well. If this was used instead of swap from a hard drive, the performance increase is so high that any latency is insignificant (5-10ms vs <1us). If it was used to hold running programs, it would be quite high.

The chipsets will probably use a PCI like assignment scheme to non local memory. Each NB's memory is assigned a handle and a command to the NB would assign a window (x pages (in some UNIX systems, 4KB per page) starting at page y) of that non local memory to an area of the local address space (the window starts at address z and is x pages long). This method would require little change to any OS, mostly in the Virtual Memory Driver. The rest of the changes are just to figure how much memory attached to each NB and some way to figure the latency incurred.

I hope this yields a better understanding.

Pet
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