Advanced Micro Devices - Moderated (AMD) Message Board

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 217.53

+1.5%

Nov 28 9:30 AM EST

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next

To: Scumbria who wrote (13616)	10/13/2000 11:28:57 AM
From: Daniel Schuh	Read Replies (1) of 275872

Scumbria, here's the dread Paul DeMone's comments on P4 at mpf. - Not too much new about P4. About 5% of the die runs at 2x the processor clock. This includes the fast integer uOP schedulers, the reg file, the bypass network, and the two fast ALUs and suprisingly, the two AGUs (address generation units). The P4 does speculatively issue int uOPs dependent on data from cache like the EV6. Unlike the EV6 (which has a predictor in hardware), the P4 always assumes that loads will hit in the dcache). Another suprise is the P4 does hardware prefetch. That is basically a piece of logic that watches the memory access stream and when it sees regularity (basically accesses with constant stride) it prefetches ahead. I am suprised this is attempted in the x86/desktop app world. I refuse to post a link publicly, he repeats some other crap in the full text. Cheers, Dan.

Report TOU Violation

Share This Post

Public Reply Prvt Reply Mark as Last Read File

Previous 10 Next 10 Previous Next