Aaron - Re: "David Taylor, Slot 1, Socket 7 and K6"
Let's start with the Pentium & K6 - These devices have 64 data pins that access external memory.
Most Pentium level PC systems have two types of external memory -
A. Main Memory (usually DRAM) that has access times of around 60 nS (16.7 MHz). This is slow compared to 200 mHz processors (Internal Clock Speeds INSIDE THE CPU). However, DRAM is relatively cheap. Main Memory generally runs from 8 MegaBytes up to 64 MegaBytes (or greater for really large workstations & servers).
B. Level 2 (L2) Cache memory - generally uses high speed static RAMs (SRAMs) with access times of 15 nS or less. this is more expensive than DRAM. L2 caches generally come in 256 KiloByte, 512 KB or occasionally 1 MegaByte sizes.
The 64 data lines are shared between these two memories. External logic in the chip set will select the L2 OR the main memory (NEVER both).
The external bus speeds of most Pentium/K6 PCs is 66.66 MHz. When a memory access needs to be performed, the INTERNAL Level 1 cache inside the CPU is interrogated to see if the memory location being accessed has a "copy" inside the internal L1 cache. If it is NOT in the L1 cache, the CPU interrogates the L2 cache. If the memory content is available there (a copy) the data is read from the L2 cache using external bus timing - 66.66 MHz (about 15 nanoseconds). During this 15 nS, the processor must WAIT for the L2 cache aceess to produce valid data. This 15 nS corresponds to about 3 clock cycles of the CPU's internal clock for a 200 MHz CPU (5 nS clock periods).
If the memory contents are not in the L2 cache, the CPU accesses the Main memory where the data will "always" exist. Because main memory is DRAM, with access times of 60 nS, the external clock speed of 66.67 MHz is TOO FAST. So, a memory read cycle is started, but a WAIT STATE (or SEVERAL WAIT STATES) are invoked by the chip set logic which essentially puta the CPU in a "HOLD" state until the 60 nansoseconds has elapsed. This could be about 4 clock cycles on a 66 MHz external clock - and as many as 12 clock cycles on the INTERNAL clock of the CPU if it is running at 200 MHz (Internal CPU CLock Speed).
As you can gleam - any data accessed externally from the L2 or main memory causes the system to slow down - the CPU just waits until valid data can be accessed - 3 clock cycles for L2 cache accesses or 12 clock cycles for main memory accesses.
If the external clock is speeded up - let's say to 100 MHz, then the L2 cache can be accessed faster IF FASTER SRAM chips are used - at least 10 nS (1/100 MHz) access time (or less). So, the L2 cache costs go up. Now, the L2 cache can be accessed in 10 nS which is only 2 INTERNAL clock cycles for a 200 MHz CPU. Basically, this is a 33% improvement - 10 nS instead of 15 nS for L2 caches.
Note main memory DRAM can change if newer types are used such as SDRAM - Synchronous DRAMS. These may also access in speeds up to 100 MHz. If they do - L2 cache amy not even be necessary since Main Memory and L2 caches would run at 100 MHz (10 nanoseconds).
Now - the Pentium II is a different animal. The Pentium II has TWO data buses - BOTH 64 bits wide. One of these buses is wired directly to an external L2 cache and it runs at one half the speed of the CPUs INTERNAL clock. For example, a 266 MHz Pentium II will read and write data to the L2 cache at 133 MHz.
The second data bus, also 64 bits, is wired to the slower main memory, just like a Pentium or K6.
(Note - this idea was first used by NexGEN about 4 years ago on their Nx586 device - BEFORE AMD bought them.)
Now, the current chip sets for the Pentium II run at 66.67 MHz clock speeds just like the Pentium and K6. So, if main memory is acceesed, they both (Pentium II and Pentium/K6) access the data very slowly with as many as 12 CPU clock cycles wasted while the data is retrieved.
However, when the Pentium II accesses its L2 cache, it can gobble up the data at 133 MHz or 7.5 nS. Thus, only 2 internal clock cycles (1/266 MHz = 3.8 nS) will be wasted. This compares to the Pentium/K6 which would have 15 nS delays (for a 66.67 external bus).
Now - if and when the Pentium II gets a chip set (440LX) that runs at 100 MHz, the CPU will still run at 266 MHz internally, and the L2 cache will run just like before - at 133 MHz - half the CPU clock speed.
Thus, L2 cache accesses WILL NOT BE SPEEDED UP for faster EXTERNAL clocks on a Pentium II. The L2 cache access remains fixed at half the processor clock speed.
Of course, main memory accesses will increase in speed if 100 MHz SDRAM chips are used.
That summarizes, in more detail, what David Taylor said. However, Taylor neglected to discuss the possible elimination of an L2 cache if a 100 MHz external clock can read main memory (SDRAM) as fast as 100 nS SRAM.
There may be subtle delays in SDRAMs that will still make use of a high speed L2 SRAM cache advantageous. At this point, I'm not sure.
Paul |
