Elmer: Ok, since you've conceded that the report Paul quoted about may be wrong.. now we get to the core of the issue.. you think they are far behind on SMP.. Fair enough. Lets see a completely opposite perspective to yours and discuss that.
From Oct 11: "AMD grabs high ground with SMP Athlon"
AMD unveiled its multiprocessor plans yesterday, and judged solely on its technical merits, the Athlon-based
SMPs that result ought to cause some late nights at Santa
Clara. And not just of a tactical nature, but strategic. If
we weren't so nasty and cynical, we'd be tempted to describe
it as a technical tour de force that bears all the hallmarks
of people who know how to build high bandwidth parallel
systems. But judge for yourselves...
SMP AMD-style looks like this: there'll be basic two way
or four way building blocks, again using the 266Mhz Athlon
bus, based on the new AMD-760 MP chipset. Level 1 cache is
exclusive, and the front-side "bus" (yes, OK, we know it's a
switch...) hums along at 4.2GBytes/second.
Nothing to worry the Alpha folks there just yet, but
Athlon's deep pipelines and other judicious design choices
- such as a dedicated snoopy bus - leave an awful lot of
headroom for the architecture. Chimpzilla also reckons that
adding an "owner" state to the cache coherency protocol also
optimizes inter-cache traffic ... but we'll throw this
one to the floor.
AMD veep Rich Heye, a veteran engineer of both the early
DEC Alpha and IBM Somerset Project (aka, the PowerPC)
-unveiled the details with a marvellous fusillade of one
liners, the most popular of which had some Intel folk
grinning: "They said we couldn't do it [Athlon]... but we
built it, we shipped it... and we didn't have to recall it."
Catching him in an off-guard moment later, Heye (a Reg
devotee, natch) pinned the blame on Intel's fetish for the
Rambus architecture. AMD's SMP uses DDR. "I haven't seen
P4," he said, "but the whole point of this is to keep
banging the memory with requests. I'll bet you that
with Rambus, most of the time those buffers are empty."
Heye made the same point, anticipating a forthcoming
clock speed bus war in the presentation: "Some people will
look at bus speeds and say, 'Aw, 266Mhz? That's as slow as sin'. But you can't just be looking at wire speeds or at clock rates - it's how you use those wires," he said.
Which is fine by us. But of course there's a lot more to
building SMPs than filling pipelines. Throughout its
succession of well-publicised recalls, Intel's front edge
server business continued to do its usual, awesome job of
providing reliable SMP racks in large numbers and to
order. That makes AMD's next challenge an operational, rather than technical issue.
But where it gets strategic and really serious for Chipzilla
is that the volumes in the low-end server business are that
much lower than in the volume desktop business. With their
respective fab capacities, AMD has, regardless of what it
might like to do, a practical ceiling for its market share.
But the two way/four way business looks a lot more
promising, and really becomes low-hanging fruit for AMD.
A successful roll-out of the first racks could see AMD
gobble up a greater proportion of the business quite
rapidly. Whether it has the operational expertise to seize
this new channel, we'll see. ®
theregister.co.uk |
