Xilinx Establishes Leadership Direction for High-Bandwidth I/O Technologies
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On tap are LDT, POS-PHY4, 3.125Gbit, Infiniband, XAUI, RapidIO, and Fibre Channel for FPGAs; Virtex-II architecture
to break 10 Gb/sec barrier next year
SAN JOSE, Calif.--(BUSINESS WIRE)--Sept. 25, 2000-- Xilinx, Inc. (NASDAQ:XLNX - news), the leader in programmable logic, today announced an aggressive plan to provide high-bandwidth interconnect technologies for its FPGAs that will break the critical 10 Gigabits per second (Gb/sec) bandwidth barrier within the next year. Users can anticipate implementing these high-bandwidth interconnect technologies in the next generation Virtex-II architecture.
High bandwidth interconnect technology is becoming increasingly necessary as FPGAs are used more and more as critical components in communications equipment. In addition to enabling much higher device performance, high bandwidth I/Os free-up package pins that were traditionally used as parallel I/Os. They also minimize switching related problems and drastically reduce power dissipation thereby enhancing device reliability in high bandwidth applications.
``The integration of very high bandwidth interconnects and the previously announced IBM PowerPC processor core within our Virtex-II architecture will offer customers the most flexible, fastest time-to-market development platform in the industry,'' said Dennis Segers, senior vice president and general manager of the Xilinx Advanced Products Group. ``The Internet economy has accelerated the need for these high-bandwidth interconnect standards. The breadth of standards that will be supported by Xilinx will ensure that system architects have flexible solutions for their emerging networking applications.'' |
