Dear Kash:
Re: "The sweet spot must be above the minimum speed grade."
This is obviously not true wrt cC0 stepping P3 was used solely to get to 1GHz. It shipped with only 933Mhz and 1GHz . The sweet spot was below this as far more 933Mhz were made than 1GHz and very few 1.13GHz. Normal rating (80C) for this stepping had a sweet spot of around 800MHz. This is the same situation wrt P4. IMHO, P4 sweet spot is < 1.4GHz (could even be the 1.2G grade as 1.2G were used as engineering samples but, the performance was underwhelming as shown in their benchmarks so they figured that they just would not sell at the prices needed given high cost of i850 mobo, and 2 sticks Rambus needed (they would steal valuable resources (RDRAM) from higher brothers)).
Thus, their ramp will look like 1GHz P3, <100K Q4 (infrastructure problems with i850), 200K Q1, 800K Q2, 2.4M Q3 (sweet spot reaches over 1.4G and DDR becomes available), 7.2M Q4 (0.13u copper finally starts making it in prod vols) for a total of 10.6M FY01. This would lead to the stated (in Intel CC) intention that P4 rev > P3 rev in some qtr in FY02. This is less than the ramp of GHz+ K7s.
Also, in high end, MHz matters less than real performance as gamers, workstation users, and power users do know about real performance and real performance per dollar and buy the higher in the first and shifting to the second when, the first is about equal given reasonable availability (Q3 and most definitely Q2 1G P3 were not reasonably available).
We shall see by the end of Q4, how this plays out with real numbers rather than speculation.
Pete |
