ALl Intel Investors - HP's Plans For Merced (And some Details)
HP is slowly releasing some details of the Merced Project being Developed with Intel. Please see the following article.
Note the mention of Merced as the engine (actually 256 Merced's) for both a Supercomputer and as an "NC"! This is quite a range of performance to be covered by one type of device. Oh well, as long as it's an Intel device!
Some glimpse of the internals of Merced are also vaguely described. The article mentions many mini-processors internal to the Merced, with the program execution scheduling handled by compilers, effectively in software, rather than by the hardware internals. Very interesting.
I wonder what the schedule will be for Merced II ???
Paul
{============================================================}
news.com
copyright (c) C|NET
HP plans around 64-bit shift
By Brooke Crothers
May 23, 1997, 5:35 p.m. PT
Hewlett-Packard (HWP) is gearing up for a
radical shift in computer architecture when it
begins using Intel's (INTC) 64-bit Merced
chip.
Intel's current processors are based on a
32-bit architecture, referred to as IA-32. The
Merced IA-64 chip architecture will deliver
drastically higher levels of performance.
HP said today it is planning two major server
lines for the chip, expected in 1999. One line
will be Unix-based, able to string together as
many as 256 Merced chips in one
supercomputer-type system. HP will also
build its own chipset to work with this system.
The other line will be based on Windows NT,
targeted at the mainstream market. These
systems will be able to take advantage of 4
to 16 Merced processors and will be based
on Intel supporting hardware, including an
Intel chipset, or group of supporting chips for
the processor.
HP also stated that Merced processors will
be used in workstations, PCs, and
"appliances" including network computers
and mobile devices. "Though we're focusing
on severs, we absolutely see applying
[Merced] to low-end desktops and the
Internet to handle Internet workloads. It will
also be suitable for Java-type devices," said
Tod Reese, general manager of open
systems software at HP.
The major point of departure for the Merced
IA-64 architecture will be in chip design and
software. Space or "real estate" on
processors which is currently devoted to
"scheduling" instructions will be moved into
software. This is a radical move since about
half the real estate on today's chips is
devoted to scheduling and can be freed up
for raw processing, Reese said.
"This is as dramatic as the move from CISC
to RISC," said Reese, referring to the move
by many manufacturers in the processor
industry over the last eight years to chips
based on the speedier RISC (Reduced
Instruction Set Computer) design.
Instead of the Merced processor, the
compiler will handle scheduling of the
instructions, according to Reese. This will, in
turn, allow the number of instruction-crunching
miniprocessors within the main processor
itself to double, greatly increasing
performance, Reese said. A compiler
prepares computer code for execution on the
processor.
|
