Dale,
<And on-die DRAM is nearly as fast as SRAM, especially if wide data paths are used to transfer content between SRAM and DRAM. >
Someone has a new definition of "nearly as fast here". In the context of modern x86 design, there is no way the latency of DRAM, embedded or not, can come even close to SRAM. The latency can be dramatically improved compared to an off-die implementation but that's about it.
<I wasn't even half serious about the potential of AMD using eDRAM in Sledgehammer however. Generally a fab is large enough that more than one process technology can be accommodated. For example, AMD could run both Aluminum and Copper in Dresden concurrently. Best guess is that, if AMD were to buy into Micron's fab, it would have processor optimized lines for production of Sledgehammer, eDRAM capable lines for production of chipsets with eDRAM, and standard DDR DRAM production lines. Best guess is that high end consumer processors (currently T-Bird class) would integrate the NorthBridge, so the chipsets would be for low end Socket-A systems, having eDRAM for their integrated Rendition GPU. >
Actually eDRAM integration pales in comparison to Northbridge integration. Northbridge integration would significantly improve performance and nearly wipeout infrastructure problems. If I were in AMD planning. I would go for a single design for 2001 - Palomino integrated with 760 Northbridge. And sell that thing as Duron or Athlon based on bus speeds and cache size (same die - burning the right fuses at final test).
This would give a strong leg up on P4, decrease cost of the solution increase the fab utilization and would be a great way to lay-in infrastructure for Clawhammer.
Since Palamino and 760 are nearly ready now, such an effort is strictly an integration issue and a product could be enabled by Q2 2001. I do not believe Intel can compete against this for 2001 given the DDR chipset for P4 is not even ready yet.
IMHO, chasing eDRAM for anything other than L3 cache would be a waste of effort in 2001 and probably 2002. By 2003, process technology could be at a point where 64MB of memory and a CPU core can possibly integrated on to a single die - at that point in time it MAY make sense to integrate eDRAM and the requisite amount of FLASH with CPU for low-end product.
Chuck |
