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Technology Stocks : Intel Corporation (INTC)
INTC 41.41+2.2%Dec 5 3:59 PM EST
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To: Elmer who wrote (115244)10/30/2000 4:45:07 PM
From: muzosi  Read Replies (1) of 186894
 
If the layout was complete then they'd be taping out now. That's like saying the wafers are out of fab and we'll be testing them by year's end.

I wish I lived that world where after "layout complete" one didn't have to run LVS/DRC and transistor level simulations, didn't have to do back-annotation for functional and timing verification. Of course one can claim that layout can't be complete without doing these but I'd submit that would be redefining the original statement.

Muzo
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