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Technology Stocks : Intel Corporation (INTC)

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Dec 5 9:30 AM EST

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To: muzosi who wrote (115248)	10/30/2000 5:14:47 PM
From: Elmer	Read Replies (1) of 186894

Re: "I wish I lived that world where after "layout complete" one didn't have to run LVS/DRC and transistor level simulations, didn't have to do back-annotation for functional and timing verification. Of course one can claim that layout can't be complete without doing these but I'd submit that would be redefining the original statement" Seeing as you would almost certainly have to do circuit changes after running your back-annotated timing files, how could you claim your layout is complete? You could claim your trial layout is complete. Perhaps he didn't want to confuse matters with the technical stuff. I can buy that. EP

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