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Technology Stocks : Intel Corporation (INTC)

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To: Tony Viola who wrote (115507)	11/1/2000 12:28:04 PM
From: Tenchusatsu	Read Replies (1) of 186894

Tony, <Dumb question: Do you mean the chipsets need to put the RDRAMs into a lower power state at times? Certainly couldn't be between accesses or the access time would go sky high.> There are several power states of RDRAM devices. Two are relevant here, active and standby. If I remember correctly, it takes a couple of 100 MHz clocks to bring a device out of standby into active state. On the 820 chipset, up to four RDRAM devices can be in active state at a time. But most systems based on 820 have 128 megs of RDRAM, i.e. at least 8 RDRAM devices on the channel. So if accesses are random and sporadic, devices will have to be juggled between active and standby states, and that increases latency. The situation worsens for larger amounts of RDRAM, i.e. more RDRAM devices. My guess is that this mechanism was designed as a trade-off between performance and power requirements (or signal integrity caused by large power draws, or whatever, I don't know). And this perhaps points back to the original notion that RDRAM may have been way ahead of its time. Tenchusatsu

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