Hi Tony Viola; Re: AMD's possible 761 chipset problem. " that workaround is one of the oldest and worst bandaids in the annals of electronics: hang a capacitor on it!"
My guess is that it is something to do with the LDT channel, on the "SADDINCLK" or one of the four "SDATAINCLK[3:0]" pins. Those clock lines (if the 751 is like the 761) free run, but are forced low by CLKFWDRST, which brings all the clocks to a known state. Glitches on those lines would be literally what was described, a clock glitch from the 761 causing the processor to hang. As to what kind of a glitch, who knows, but there is no way in hell they are going to be able to fix it with a capacitor. In any case, the LDT bus is the connection between the processor and the 761, DDR SDRAM has nothing to do with it.
To get an idea of what the technical issues are on the LDT, you have to read the AMD specs on the 751 chip. The problem is likely a transmission of data from clock domain to another. Basically, the system timing is partly ROM based. From reading the following, it should become obvious to the typical engineer that the 761's LDT interface can have problems that are relatively cheap and easy to fix. The external part that would fix the timing would be an external ROM, not a capacitor:
AMD Athlon(TM) Processor SIP Mapping. The AMD-751 system controller is repsonsible for supplying initialization values to the AMD Athlon processor that are a function of physical AMD Athlon system bus length, SYSCLK frequency, and processor clock multiplier. These values must be loaded prior to any AMD Athlon system bus transactions and are supplied through the SIP protocol. The AMD-751 implements two modes - production and debug. During reset, if ROM_SCK is pulled High (debug mode), the SROM supplies the SIP packet to the AMD-751. If ROM_SCK is pulled Low, (production mode), the SIP packet is generated internally. (page 71 of 236)
amd.com
If it were a problem of this sort, that would also explain why the sample boards didn't have problems. This sort of timing issue only show up when you put things into production. All in all, the sort of thing that the chip makers keep secret, and nobody gives a dang about most of the time.
This would also explain why the problem is restricted to the DDR2100 boards, while the DDR1600 boards run fine. Since the 761 is a "synchronous" chipset, the FSB has to run at the same frequency as the memory interface. The two FSB frequencies will take different adjustment values, and the 200MHz FSB is already well tested. So if the LDT fails at 266MHz, then you can't run DDR at 266MHz either. And this is the introduction of 266MHz LDT chips by AMD as well as DDR.
In addition, you can also see how it is that different manufacturers could fail to see the problem, as it will be dependent on the routing of the FSB.
As far as the timing of the DDR roll out, I approve. Volumes should be low in the rollout of a new memory technology, so the scrap costs are reduced if there are problems. But they needed to get out of the realm of DDR vapor. The biggest problem for AMD is likely to be excessive demand.
-- Carl |
