iNTEL has Glitches in i815 chipset, especially #4 below
Intel i815 Chipset Memory/Graphics Controller Errata for current stepping (A2): intel.com
#1. (insignificant)
#2. System Bus Snoop Logic Erratum
Problem: Under specific sequence of bus cycles, data from the wrong address may be returned to the graphics
controller. This can occur if the following three conditions align:
1. Back-to-back ADS# on the system bus
2. PHOLD (ISA Master) access on the hub interface
3. External graphics AGP snoop OR internal graphics cacheable BLTs/Store DWORD.
Implication: If the data from the wrong address is returned to the graphics controller, either graphics corruption or system hang can occur.
Workaround: None
Status: This Issue has only been observed in a System Validation Environment with a specific focus test. This
issue has not been observed with any real applications tested. There are no plans to fix this erratum.
#3. Asynchronous Screen Flip Erratum
Problem: When the Intel® 815 chipset A-2 step is configured for asynchronous screen flipping, under certain
timing-dependent circumstances the display engine may temporarily read pixel data from a random memory location.
Implication: When changing display surfaces using the asynchronous screen flipping, subtle display corruption is seen in the form of short, somewhat random colored, horizontal lines along the left side of the screen.
Workaround: Driver version 4.1.1 does, and future versions will, disable asynchronous screen flipping for commonly
used 3D resolutions.
Status: There are no plans to fix this erratum in silicon.
4. System Memory Data Line Noise Erratum
Problem: When the Intel® 82815 A-2 step GMCH has multiple system memory data lines transition from low to high, a glitch can appear on non-switching data lines.
Implication: The erratum is amplified by trace impedance and discontinuities on the motherboard and DIMM. When measured at the SDRAM pin, it can violate the published Vil specification of SDRAM components in the
valid timing window. In this case, incorrect data could be clocked into the SDRAM causing data corruption.
Workaround: To minimize amplification of the glitch on the board:
•Follow published design specifications detailed in the Intel® 82815 Chipset Platform Design Guide, dated June 2000, Order Number 298233-001, para 5.2 and 5.4. For the 82815E, follow published design specifications detailed in the Intel® 82815E Chipset Platform Design Guide, dated June
2000, Order Number 298234-001, para 5.2 and 5.4.
•Implement buffer strength and System Memory RCOMP settings documented in the Intel® 82815 GMCH BIOS Specification Update, rev 0.76.
Status: There are no plans to fix this erratum in silicon.
With Intel, its good enough to "minimize" glitches (their word, not mine) by reducing "amplification" of glitches on the motherboard. DON'T ASK INTEL TO FIX THE GLITCHES IN SILICON!
Petz |
