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Technology Stocks : Intel Corporation (INTC)

INTC 38.72

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11:07 AM EST

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To: Joseph Pareti who wrote (118393)	11/19/2000 5:57:07 PM
From: milo_morai	Read Replies (1) of 186894

Because it's not real world, Also remember your looking at a SDRAM comparision, and P4 stinks. DDR/Palamino is going to wipe P4 all over the floor, based on everything we are seeing. Milo P4 errata so far is 40 ftp://download.intel.com/design/pentium4/specupdt/24919901.pdf Here's a few samples INTEL ® PENTIUM ® 4 PROCESSOR SPECIFICATION UPDATE 15 N21. MCA Error Code Field in IA32_MC0_STATUS Register may become out of Sync with the Rest of the Register Problem: The MCA Error Code field of the IA32_MC0_STATUS register gets written by a different mechanism than the rest of the register. For uncorrectable errors, the other fields in the IA32_MC0_STATUS register are only updated by the first error. Any subsequent errors cause the Overflow Error bit to be asserted until this register is cleared. Because of this erratum, any further errors that are detected will update the MCA Error Code field without updating the rest of the register, thereby leaving the IA32_MC0_STATUS register with stale information. Implication: When this erratum occurs, the IA32_MC0_STATUS register contains stale information. Workaround: None identified Status: For the steppings affected see the Summary of Changes at the beginning of this section. N22. Processor may Hang on a Correctable Error and Snoop Combination Problem: The processor will hang whenever a Read-For-Ownership (RFO) or Locked-Read-For-Ownership (LRFO) hits a line in the L2 cache and also receives a correctable error. A boundary condition in the error correction logic prevents the processor from issuing further transactions on the system bus and the processor will hang. Implication: When this erratum occurs, the processor may hang. Workaround: None identified Status: For the steppings affected see the Summary of Changes at the beginning of this section. N23. The IA32_MC1_STATUS Register may Contain Incorrect Information for Correctable Errors Problem: When a speculative load operation hits the L2 cache and receives a correctable error, the IA32_MC1_STATUS register may be updated with incorrect information. The IA32_MC1_STATUS register should not be updated for speculative loads. Implication: When this erratum occurs, the IA32_MC1_STATUS register will contain incorrect information for correctable errors. Workaround: None identified Status: For the steppings affected see the Summary of Changes at the beginning of this section.

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