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Technology Stocks : Advanced Micro Devices - Moderated (AMD)

AMD 213.43

+6.2%

Dec 19 9:30 AM EST

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To: Daniel Schuh who wrote (20526)	11/26/2000 9:21:00 AM
From: fyodor_	Read Replies (2) of 275872

<Daniel: This stuff about P6-optimized software is hooey. > No it isn't. The P5 and P6 are very different architectures. The P5 has 2 integer pipes, but only 1 fp pipe. This has serious implications for issuing fp instructions. Basically, on the P5, the fp order didn't matter all that much (ignoring the non-pipelined instructions), whereas you can get a major IPC increase on the P6 by considering the two P6 fp pipes. On the other hand, the P5 had very cheap FXCH. There are also other differences. For example, when a 16bit register write is followed by a 32bit register on the P6, the read stalls until the write is retired. This doesn't happen on the P5. This is one of the things that made the P6 look bad on mixed 16/32 bit code. Additionally, the P5 had a relatively mild penalty for misaligned data compared to the P6 (which had 2-4x the penalty in cycles). Now, I'm not am expert coder like Steve Porter - far from - but there are many very important differences to consider when writing code for the P6 core. And to say that all "this stuff" is "hooey", well... I disagree ;) -fyo

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