<With current flip-chip packaging, the active area of the silicon is on the heat sink side of the package, right?>
Not exactly. Active transistor area is on the surface
that faces the package substrate, or pin side.
The heat sink is attached to the other side of chip.
The chip itself is about 0.8mm thick, therefore the
heat must be conducted across the silicon.
Now, P = k * S * Dt/Dx, where
P - dissipated power, Watts;
k is the thermal conductivity
(0.8 W/cm/C for silicon),
S is the chip area, cm2,
Dt is the temperature difference C,
Dx is the thickness of the chip.
Assuming 100W uniformly on a 1 cm2 chip of 0.1cm thick,
we can get the temperature difference across
the die:
Dt = P * Dx /k /S = 100*0.1/0.8/1=12 C
For a thermally bad chip layout with "hot spots",
the local junction temperature is proportionally
higher: if a local power density is 200W/cm2, the
hot spot will be about 24 C above the outer chip surface
temperature. Therefore the Si-28 claims look slightly
exagerrated - with 50% better conductivity you can
shave only few C, and not anywhere close to 30.
Of course, everything depends on their definitions
and power density assumptions...
Regards,
- Ali |
