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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 214.990.0%Dec 26 9:30 AM EST
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To: THE WATSONYOUTH who wrote (21774)12/7/2000 12:04:35 PM
From: pgerassiRead Replies (3) of 275872
 
Dear Watsonyouth:

SOI places the active regions of a chip in tubs of SiO2. This reduces the parasitic capacitance and substrate leakage that occurs. Both contribute to a lowering of the power required for CMOS logic circuits. Using a low-K dielectric for these tubs would reduce even further the power required.

If the chips are limited by how much heat they dissipate, reducing the amount of power used and thus, heat generated, the logic can then run faster. Remember that energy used per transition is approximately C*V^2/2 where V is the delta voltage between high and low logic states and C is the total capacitance of the connection being transitioned. By reducing C, the heat dissipated goes down proportionately. By reducing the leakage, another heat source is eliminated (I have heard this may account for up to 10% of the power dissipated in a CPU).

Thus, SOI itself can generate some decent gains. It just depends on what one thinks is a decent gain.

Pete
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