IBM unveils 0.13-micron process technology
Semiconductor Business News
(12/11/00 10:15 a.m. PST)
EAST FISHKILL, N.Y. -- Propelling itself back into the technology race, IBM Microelectronics here today officially announced its new 0.13-micron process technology.
IBM's 0.13-micron technology, called CMOS 9S, is a high-speed process complete with some new and advanced features, such as copper-interconnects, silicon-on-insulator (SOI) transistors, and low-k dielectrics.
The baseline technology was co-developed as part of alliance between IBM, Germany's Infineon Technologies AG, and Taiwan's United Microelectronics Corp. (UMC).
The process falls under what companies call the "WorldLogic" alliance, which was announced 10 months ago to develop common process technologies for 0.13- to 0.10-micron logic ICs with integrated mixed-signal circuitry and embedded DRAM.
Last week , in fact, IBM, Infineon, and UMC announced they have begun fabricating advanced ICs with a new 0.13-micron process technology that's now "production ready," meaning it's widely available to customers.
IBM today said its CMOS 9S process is in pilot line production at the company's Semiconductor Research and Development Center in East Fishkill, N.Y. In early 2001, IBM intends to introduce chips based on the technology, which will be produced in its advanced, high-volume fabs in Burlington, Vt.
"Our new chip-making recipe integrates more complex, high-performance ingredients onto a chip than ever before," said Bijan Davari, IBM Fellow and vice president of technology and emerging products for IBM Microelectronics. "The integration of SOI, copper and low-k insulation offers a powerful combination of technologies which maintains our two to three-year technological lead," he said.
The CMOS 9S technology features several new and advanced technologies, including what the company claims is the world's smallest SRAM memory cell in production at 2.16-square microns.
CMOS 9S is also said to be the only 0.13-micron technology to take advantage of the performance benefits of SOI. When combined with up to nine layers of copper-interconnects in the process, SOI can be used in several high-performance, low-power applications, such as wireless communications, and others, the company said.
CMOS 9S also uses low-k dielectric insulation, thereby reducing electrical interference between wires that can hinder chip performance and waste power |
