SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 257.55+1.5%2:26 PM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: combjelly who wrote (22462)12/14/2000 10:17:54 AM
From: fyodor_Read Replies (2) of 275872
 
combjelly: Considering that the core was originally supposed to be only some 10% larger than a pony core, 100mm^2, more or less, means a 1 meg. L2 cache, assuming a similar cache to the current Athlon. Since rumor has it that it will use the EV6 bus, I would rather see a much smaller
cache and it relying on an eCache chipset for maximum performance.


I would rather see the smaller cache and an integrated memory controller, resulting in a diesize of around 100mm2 ;).

-fyo
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext