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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 231.80+1.7%3:59 PM EST
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To: Goutam who wrote (22322)12/14/2000 2:41:31 PM
From: EricRRRead Replies (1) of 275872
 
Read this story with a critical eye:

Intel also took a look at the execution trace cache, a feature designed to compensate for the long instruction pipeline by caching only decoded micro-ops. It's a key part of the memory subsystem that reduces decode latency, and engineers were leaning toward making it bigger rather than smaller, Boggs said.

Compromising, Intel kept the size of the trace cache at 12,000 instructions and developed in instruction a micro-op "compression algorithm" so that micro-ops can be stored in the cache using fewer bits. That gave the execution trace cache "essentially the same performance and less die size," Boggs said.

Translation- The Trace cache didn't work as well as we thought, so we needed a patch.

To compensate for the L3 loss, Intel doubled the density of the L2 cache to 256 kbytes. It also cut the L1 cache size in half to 8 kbytes and reduced its load capacity to one per clock, thereby reducing latency, Boggs said.


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