Plastic chips, single-electron devices emerge from the lab
By Peter Clarke
EE Times
(12/15/00 05:09 a.m. PST)
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SAN FRANCISCO — Plastic semiconductors and single-electron transistors are fast moving from the lab into the realm of products, according to scientists at this week's International Electron Devices Meeting. Research has heated up in both fields, yielding the promise of commercial parts that can challenge CMOS devices within five years.
Papers at IEDM told of plastic circuits on flexible substrates, circuits that can be built with an inkjet printer without the use of toxic materials, and highly efficient memory and logic circuits that store information and switch under the influence of a single electron.
The successful scaling of CMOS process technology has become predictable, almost mundane, and is certainly expected to continue. But alternative technologies like those showcased at IEDM have a role to play when Sematech's International Technology Roadmap for Semiconductors hits some of the quantum roadblocks now foreseen in its path.
For both single-electron transistors (SETs) and plastics semiconductors, deployment — probably in niches alongside successful CMOS products — is likely by the middle of this decade, scientists said.
"There's not enough reason to go to single-electron type circuits right now, not against the progress being made by CMOS," said Kazuo Yano, a senior researcher for the Hitachi Central Research Laboratory. "But there may be applications and niches where we can enter and show benefits in the post-PC era — perhaps as a very low-power memory for the mobile phone — which we can use as a beachhead to get into other applications."
When asked how long that might take Yano said, "Within five years, perhaps."
Even in the area of computer simulation, which strives to model devices and process steps, the movers and shakers are starting to think outside the CMOS box.
"We're starting to look beyond the end of the road map," Robert Dutton, a professor at Stanford University, said at an Avanti Corp. meeting held during IEDM. "Is there a replacement transistor? What about 3-D integration, what about process integration of new materials?"
Changes afoot
Dutton spoke of an explosion of complexity that will tax the modeling community even within the next few years, when mainstream CMOS still reigns. But he also said that the technical-CAD community must prepare for the post-CMOS era, be it in the form of silicon-based quantum devices, such as SETs, or organic semiconductors.
Two presentations at IEDM showed off the current capabilities, and some of the limitations, of plastic semiconductors.
A paper from Penn State University reported on the fastest organic circuits yet fabricated on flexible polymeric substrates, while a team from University of Cambridge, England, reported on polymeric transistors laid down using inkjet printing. The English group is closely associated with Seiko Epson and Plastic Logic Ltd. in Cambridge, a recently formed startup devoted to building plastic semiconductors.
The team from Penn State used a transparent, colorless polyethylene naphthalate (PEN) film, 75 microns thick, as the substrate and the small-molecule hydrocarbon pentacene as the active semiconductor material.
The fabrication methodology required photolithography and a reverse deposition process, with a nickel gate laid down first to avoid high-temperature processing degrading the pentacene. Nevertheless, the resulting devices — including transistor arrays, inverters, ring oscillators, frequency dividers and differential amplifiers — performed well.
Typically the transistors had 20-to-25-micron gate lengths, and a -25-V voltage scheme. The ring oscillators had a propagation delay of 37 microseconds per stage, corresponding to a 2.7-kHz frequency. For a 1-square-centimeter array of 200 transistors, the maximum clock frequency for digital circuits was 1.1 kHz and yield was better than 90 percent, the team reported.
Chris Sheraw, who presented the paper, made the point that this was a good result considering the devices were not fabricated in a clean room.
The use of pentacene gives electron-mobility values of around 1 cm2 per volt-second. Although this number is low compared with the amorphous, polycrystalline and single-crystal forms of silicon, it allows a number of potential applications to be considered, Sheraw said.
The use of the transparent flexible substrate is in keeping with one of the primary applications foreseen for plastic electronics, Sheraw said: display driving. "But we're also thinking of RF identification tags," he said, "and smart cards may be possible."
Sheraw was optimistic that further refinements are yet to come: "I think we can improve the speed quite a bit, by moving the threshold voltage." He also said it should be possible to reduce the operating voltage to 12 V.
The second plastic electronics paper was from a team from the Cavendish Laboratory at the University of Cambridge and Epson Cambridge Laboratory. Takeo Kawase presented results for top-gate thin-film transistors fabricated using a Seiko-Epson high-resolution inkjet printer.
The source, gate and drain are all made from polyethylenedioxythiophene (Pedot) inkjet printed onto the substrate. The semiconductor layer is a conjugated polymer of fluorine-bithiophene copolymer and the insulating polymer is polyvinylphenol (PVP). Both are spun onto the surface.
Inkjet transistors
Although inkjet printing has been used to fabricate light-emitting polymers and large-area displays, this is believed to be the first time it has been used for printing small transistors.
However, the Cambridge team did resort to using a photolithographically defined 5-micron-wide polyimide layer as the starting point for the 5-micron gate of the devices. So the complete device was not entirely inkjet printed. Nonetheless, on/off current ratios of 10,000 and electron mobilities of 0.02 cm2/volt-second were obtained.
Kawase emphasized the low-cost and environmentally friendly nature of inkjet printing, which uses no heavy metals or toxic gases and has limited need for water and cleaning.
"Any mobility above 0.01 is interesting," said Kawase's co-author, Henning Sirringhaus, a lecturer at Cambridge University and also the technical director of Plastic Logic. "You can think about active-matrix drive. It's true that the range of applications for materials with a mobility of 0.02 is narrow at the moment, but one of the directions for the company [Plastic Logic] is to do materials searching."
For those that would like to combine the high mobility of pentacene with inkjet printing, Sirringhaus observed, "Unfortunately, pentacene is not soluble."
Sirringhaus said that while the paper reports on 20-V operation, polymer transistors could also work at 10 V with an optimized structure.
One question mark hanging over polymer-based electronics is how long they last and how devices and materials may degrade or wear out.
"The issues are no different than LEP [light-emitting polymers]," Sirringhaus said. "With proper encapsulation you should be able to get 10 years. But lifetime, lifetime optimization, wear-out mechanisms — that's why the company has been set up."
Sirringhaus declined to speculate on when plastic logic might become a commercial reality. But he said that over the last few years — and especially with the award of this year's Nobel prize to three chemists whose work led to the development of conducting polymers — "the field has won a lot more credibility." Those winners were Hideki Shirikawa, Alan Heeger and Alan MacDiarmid.
Single-electron advances
The breadth and silicon compatibility of the low-electron-count devices usually called SETs are rising fast, according to research reported at IEDM. Circuits built around transistors that switch on and off based on the movement of a few electrons — or just one — should have tiny power consumption compared with conventional devices, which are based on the movement of tens or hundreds of thousands of electrons.
Over the last 10 years, numerous SETs have been demonstrated, but they have usually required exotic materials such as gallium arsenide, ultralow temperatures or a construction far different from conventional silicon structures. On the other hand, they also use process steps that would be low in cost to manufacture.
Numerous SET papers in the nanoelectronics session at IEDM showed how researchers are overcoming some of those problems. Among the advances reported were room-temperature devices in silicon from Hitachi, a "half-adder" circuit from NTT Basic Research Laboratories, room-temperature SET logic from Toshiba and a single-electron charge-coupled device, again from NTT.
"They've built logic circuits, that's a huge step," said Mark Law of the University of Florida, the general chairman of this year's IEDM.
The team from NTT built an elemental circuit using SETs fabricated with a silicon-on-insulator process. The transistors carried out "half-sum" and "carry-out of the half-adder" operations. In theory, once one or two devices can be connected, with well-controlled gate and total capacitance it should be possible to build much larger circuits.
The NTT circuit uses a pass-transistor logic scheme, which is said to be appropriate because of its compatibility with low-power and low-voltage schemes. However, like a lot of single-crystal-silicon SETs, it required a low temperature to operate: 25 Kelvin.
By contrast, the transistor described in a paper by a Hitachi team led by Yano operates at room temperature. It's a memory transistor that is compatible with the architecture Yano disclosed in a prize-winning paper on a 128-Mbit single-electron DRAM, given at the International Solid-State Circuits Conference in February 1998.
To operate at room temperature, this so-called SESO memory transistor uses the Coulomb blockade effect within a 2-nm layer of polycrystalline silicon. The quantum-dot storage traps are grain boundaries in the polysilicon.
The primary effort of the latest research was to reduce the leakage current. It is reported as 1.1 x 10-19 amps, claimed to be the lowest in polycrystalline thin films. The trick is to mount the polycrystalline silicon film on insulating silicon dioxide and separate it from its conventional gate by the same material, effectively constraining electron-trapping sites in one dimension.
This translates to one electron leaking from the transistor every 100 milliseconds, yielding a projected refresh time of 3,000 seconds without the use of a memory capacitor. Yano's team concluded that the SESO is a candidate for 4-Gbit or larger post-DRAM memories fabricated in sub-100-nm (0.1-micron) process technologies. |
