Steve, I don't think RDRAM will be used yet. The author may have extrapolated from this 9/15/00 article. The thinking is that the new SUNW IIe would be using SDRAM technology from RMBS, but the RMBS is never mentioned directly so is a dangerous assumption.
Sun Finally Ignites UltraSPARC IIe
By Steve Leibson
Announced last year at Embedded Processor Forum, the UltraSPARC IIe is finally ready to rock and roll. The integrated processor incorporates an execution unit based on Sun's SPARC V9 architecture, with a floating-point unit and VIS (visual instruction set) multimedia extensions; independent 16K instruction and data caches; a unified, four-way set-associative 256K L2 cache; a 32-bit 66MHz PCI bus controller; and a PC-100 SDRAM controller with ECC. The UltraSPARC IIe's SDRAM controller can manage four single- or dual-sided buffered or unbuffered SDRAM modules, for a maximum current capacity of 2GB. Power-management capabilities include a software-controlled clock that can operate the core at full, half, or one-sixth speed, with attendant linear power reductions at each drop in clock rate, from 13W at full speed to 2.5W at one-sixth speed. In addition, the memory controller can put the SDRAM into self-refresh mode, placing the processor into what might best be called a daydream state.
chipanalyst.com
Another comment was from Electronic news in November 2000:
Sun Microsystems Inc. has clearly stated that it has no intention of using RDRAM for its flagship microprocessor line, the UltraSPARC.
"We looked at Rambus years ago and decided it was not for us, and it looks like Intel is deciding the same thing,” said Anant Agrawal, vice president of engineering of the SPARC Technology Business of Sun. However, Sun is using Rambus for its MAJC graphics processor, Agrawal noted, but he said Sun was not using that chip in any of its products. Intel’s MTH was devised as a means to interface Intel’s 820 chipset to SDRAM memory. It was required because the 820 was originally designed to interface to RDRAM, but needed to link to SDRAM due to the prohibitively high cost of RDRAM. "
electronicnews.com
That being said, SUNW has an article date 2/00 on Wirespeed Multimedia Computing at sun.com
The older MAJC 5200 chip will use an 800mHz Rambus interface for its stream memory controller. See page 7 of 50. It mentions the D-RDRAM on page 8 and 47.
I think SUNW wants to use the RMBS RDRAM technology, but not at the present price. Maybe there negoiations to lower the license revenues, but neither (SUNW or RMBS) would ever admit to that.
Jack |
