SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 213.43+6.2%Dec 19 9:30 AM EST

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: jcholewa who wrote (27047)1/31/2001 7:47:55 PM
From: TechieGuy-altRead Replies (2) of 275872
 
I should point out that the fact that the total cache of the system is now 768KB instead of 384KB could easily account for a greater than linear performance increase.

If I understand what you are implying (greater cache = lower miss rates etc.), then that is not true. Each processor still has 128+256K cache. The hit rate of each processor is still limited by its own cache size.

I would guess that the performance improvement is from the lower total processor stalls as compared to a single Athlon processor system processor stalls * 2.

This is of course due to better utilization of the memory bus (while one processor is crunching data the other is accessing the memory- which otherwise would have been sitting idle in a 1P system).

TG
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext