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Technology Stocks : Intel Corporation (INTC)

INTC 40.56

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Nov 28 9:30 AM EST

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To: Paul Engel who wrote (126558)	2/3/2001 8:09:46 PM
From: Elmer	Read Replies (2) of 186894

Re: "[Monica to Paul]Ever hear of cache coherency?" The only was to avoid cache coherency delays is to eliminate cache and it should be noted that the P6 style shared bus allows the other processors to snoop the addresses as they appear on the bus. The EV6 architecture requires at least 1 clock to translate the address on one port and present it to the other[s], plus added delays for snoop stalls and snarfs(Yes there is such a thing as a snarf). The proof is in the pudding. The P6 SMP bus worked from the very first A-0 stepping of the 440FX. The EV6 SMP architecture just plain doesn't work and AMD has given up. EP

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