Paul, from your Sharky quote:
<So in order to make an MP Athlon chipset, AMD had to put two EV6 busses. This increases the chipset die size and pin count, which thereby increases the chipset's cost. AMD has a shared bus architecture relying on LDT planned for their K8 series processors.>
Sharky is right in that multiprocessor Athlon chipsets require a separate EV6 interface for each processor, which complicates chipset design.
However, Sharky is wrong in saying that LDT is a "shared bus architecture." LDT is actually going to be a "switched fabric" architecture, which is going to be the wave of future SHV servers, frankly speaking. Each LDT connection is point-to-point, like EV6, but LDT is more sophisticated and has a higher bandwidth-per-pin, which allows for fewer pins.
Of course, just because AMD has nice LDT foils doesn't mean they'll execute flawlessly on the technology. Based on the numerous server delays we've seen from Sun, Alpha, AMD, and of course Intel, I have to wonder whether AMD has what it takes to drive LDT into high-end servers.
Tenchusatsu |
