Tench, re:"I expect dual-Foster workstations to beat the pants off of dual-Palomino workstations in pure performance."
How can they do this still using the 0.18u process? The die size, 217mm is already huge and the current P4 has way-too-small cache sizes for SMP. The P4 needs to have a very fast access to main memory because of its cache limitations, but in an SMP system that bandwidth is shared.
In another post you mentioned that perhaps a 2 GHz Foster would be released. Since the 2 GHz Foster would have to use SOI techology, I can't imagine more than samples until Q4. It would still have an enormous die size on 0.18, but heck, if it costs $150 to make and sells for $800, I guess its worth it. But I still think 2 GHz Foster would underperform dual 1.5 GHz Palominos by a considerable amount due to the memory bandwidth dependency. Guess what, that means that a 2 GHz Foster would not sell for $800. ;^)
I figured out that Foster must use SOI from this link: heise.de
Here's the Babelfish translation:
The other extreme in Intels technique port technikportfolio is on Wednesday in
the footlights: The chip market leader wants to give an idea of the techniques,
which enable on base of the 0,18-µm-Prozesses the operation of the arithmetic
and logic units of the Pentium to 4 with an internal clock of 4 GHz. A further
lecture points out, how the SOI technique (silicone on Insulator) can accelerate
the 0,18-µm-Prozess around 14 per cent. ( as / c't)
Petz |
