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Technology Stocks : Advanced Micro Devices - Moderated (AMD)
AMD 213.43+6.2%Dec 19 9:30 AM EST
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To: fingolfen who wrote (28341)2/13/2001 6:13:38 PM
From: pgerassiRead Replies (3) of 275872
 
Dear Fingolfen:

I was under the impression from my professors and others on these threads here that the major determinant was defect density of the wafers involved. Logic areas are rarely redundant compared to memory areas. Since cache of P4 is smaller than the amount in P3, the extra room of P4 is entirely made up of logic (this includes connections). Thus, a simple formula for probable yield is exp(-log(defects per wafer / number of die per wafer)) times some constant(other factors).

Since P4 is about 2.3 times the size of P3, there is roughly only 40% as much P4 die as P3 die per wafer. Assuming that the constant is smaller but, still close to, than 1.0, a 90% yield of P3 becomes 77% yield for P4. Similarly, a 80% P3 yield becomes 62% P4 and a 70% P3 becomes 41% P4 yield. Given that the cache area percentage of the P4 is also smaller than the P3 and that other factors also increase the risk of failure (more to go wrong), the calculations are giving the benefit of the doubt to P4 yields.

Therefore the calculations you cite as "so ludicrous" are themselves laughable unless there are significant differences to the actual yield formula. Prove your case with real data and constants in your calculations. Otherwise, we may take it that you are guessing (CWAG).

Pete
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