Scumbria,
Are you suggesting that AMD put PCI onboard too?
No, nothing else for now, just the memory controller.
It is a mistake to use an onboard memory controller, because it ties the chip to a particular type and speed of DRAM,
That's true, but once a year or so, that we see a newer memory speed, AMD can just upgrade the CPU. The speed of core revisions seems to be at least this fast, even faster.
AMD has always been limited by the weekest link of the CPU / northbridge combination, and this way, AMD will have their destiny in their own hands. After 750, 760, 760 MP, I think AMD has enough experience inhouse to pull it off.
As far as upgrades go, there is no reason to have speed timing (or multiplier) for the memory speed that can be set, so that the processor is compatible with older, slower memory. As far as faster memory than the CPU can support, I don't know what the point of that would be.
and it makes MP much more complex.
If Sledge has 2 cores, there is not much point in having more than 1 of those for desktop through workstation market. In server market, LDT is promising to actually simplify this.
I could see a high end system with daughtercards, each one having a Sledgehammer processor + 2 to 4 DIMMS of memory, with the daughtercard being actually the LDT connection. To me, this is a lot simpler than current solutions.
Another way would be to make a system with a number of relatively cheap simpler motherboards, possibly in 1 rack case, connected with LDT.
Or another, more traditional way, to make a motherboard with 2 (or even 4) SledgeHammer sockets, with corresponding number of memory channels. Even this approach is simpler than current multiple memory channel systems, since they all go to a single northbridge, whereas with CPUs + onboard memory controller, each CPU would be connected to only its own channel (each channel completely independent from the channel of other CPUs).
Better to use the transistors for cache.
It may or may not be true. One way to determine this would be to start with how many net additional transistors you need for the memory controller. By net, I mean subtract the bus interface transistors from current CPU, subtract bus interface transistors from the memory controller, add this to the CPU, and add LDT transistors. How much cache worth of transistors would you be adding? 128K? 256K? I don't know.
Now, suppose you have a Sledgehammer with 512 or 1 MB L2. How much more performance would the 128K or 256K of L2 add? Not much IMO. But on the other hand, if you reduce the memory latency by say 4 cycles x (approx) 15 multiplier, you get 60 CPU cycles gain for each new off chip access. My WAG is that on-board memory controller would have higher performance.
Joe |
